SAVE the DATE TAPIA 2020 Dallas,TX September 16-19, 2020

2019 Tapia Conference

BRISC-V: A RISC-V Open-Source Architecture Design Space Exploration Toolbox

Friday, September 20, 2019 — 10:40AM - 11:40AM


With the introduction of the RISC-V instruction set architecture (ISA) and its rapidly growing ecosystem and community, there may be a unique opportunity to broaden participation in computer architecture design to groups who have been traditionally severely underrepresented. The RISC-V being an open, royalty-free, ISA with many extension specifications, it offers a high degree of customization and represents an attractive option for many applications, ranging from machine learning accelerators to secure computer systems design. In this workshop, we will present the BRISC-V toobox - the Boston University RISC-V based architecture design exploration suite for education and research. BRISC-V is comprised of different processor architectures, a graphical user-interface (GUI) tool to automate fast complete system generations, and a RISC-V assembly simulator. During the session, we will (1) introduce the BRISC-V tool, (2) show its functionalities, and (3) run hands-on design exploration examples with the attendees.

Included with the BRISC-V Tool suite are (i) different complexity RISC-V cores (e.g., single-cycle core, multiple-cycle, and reconfigurable pipelined), (ii) a programmable memory system with reconfigurable multi-level cache subsystems, (iii) a parameterized interconnect network, (iv) BRISC-V explorer GUI for automatic synthesizable Verilog core and multicore system generation, and (iv) the BRISC-V simulator for software RISC-V instruction emulation. BRISC-V is an in-browser tool, therefore, it requires no installation and avoid all OS dependencies for an easy, fast, and intuitive use of the tool. It allows participants to experiment with the RISC-V ISA features and to quickly bring up complete and fully working architectures..

Workshop Presenter:
Michel Kinsy, Assistant Professor, Boston University